1. Field of the Invention
The present invention relates to a high frequency amplifier circuit that permits variable gain control, and, more particularly, a high frequency amplifier circuit that prevents noise figure degradation while retaining gain linearity and allows the number of elements to be reduced.
2. Description of the Related Art
The implementation of a high frequency circuit by means of a silicon or compound semiconductor chip has been proposed. More particularly, as cellular phones, portable information terminals, and so forth, have become widespread, the development of low-cost silicon chips mounted with high frequency circuits that can be employed in microwave bands such as 2 to 40 GHz, for example, has progressed.
Variable gain power amplifiers are employed in various places in high frequency circuits. However, in order to implement such a power amplifier in a silicon chip, the need for noise figure (NF) degradation suppression, a linear gain characteristic, a reduction in the number of elements, and so forth, must be satisfied.
FIG. 1 shows a constitutional example of a general high frequency circuit. The output F1 of the high frequency circuit 10 that performs predetermined processing on a high frequency signal F0 is input, via a matching circuit 12, to an amplifier circuit 14 capable of gain control. A signal Fout, which is amplified with the gain controlled by means of a gain control signal GCNT, is then outputted. The matching circuit 12 is a circuit for impedance-matching the output F1 of the high frequency circuit 10 such that the output F1 is optimized in accordance with the relationship between the high frequency circuit 10 and the amplifier circuit 14, whereby reflection of the high frequency signal is prevented.
FIG. 2 is a circuit diagram showing a conventional example of a gain control amplifier circuit. In this conventional example, a variable attenuator 16 is provided upstream of an amplifier circuit 18 that comprises N-channel transistors Q30 and Q31 such that the amplitude of the input F2 from the matching circuit 12 is variably attenuated by the variable attenuator 16, thereby controlling the gain of the amplifier overall. A first bias voltage Vbias1 is connected via a resistor R1 to the gate of the transistor Q31 and a second bias voltage Vbias2 is connected via a resistor R2 to the gate of the transistor Q30, such that the gain of the amplifier circuit 18 remains fixed. The variable attenuator 16 is constituted by a plurality of pie-shaped attenuation circuits 20 and 22 that are each constituted by respective resistive elements R1 to R3 and R4 to R6 respectively, such that the attenuation amount can be variably controlled by the switches SW11 and SW12. Switches SW11 and SW12 are each formed by a switch that is constituted by an N-channel transistor, for example. When switches SW11 and SW12 are both connected to attenuation circuit 20, the signal is attenuated at the attenuation rate of attenuation circuit 20. When SW11 and SW12 are both connected to the attenuation circuit 22, the signal is attenuated at the attenuation rate of the attenuation circuit 22.
An attenuator provided upstream of the amplifier circuit as mentioned above is also disclosed by Japanese Patent Application Laid Open No. H8-288791, for example.
In the attenuator-equipped amplifier circuit shown in FIG. 2, a high frequency input signal F2 is attenuated by the attenuator 16 at the attenuation rate of the attenuation circuit 20, 22 selected by the switches SW11 and SW12 before being supplied to the gate of the transistor Q30 of the amplifier circuit 18 and then amplified with fixed gain. Therefore, the attenuation rate of the attenuator can be controlled linearly by performing control by means of the switches SW11 and SW12, and, as a result, the input signal F2 can be amplified with linear gain.
However, when the amplifier circuit shown in FIG. 2 is used in a low frequency band, the resistive elements of the pie-shaped attenuation circuits become a source of noise for the high frequency signal F2 in a high frequency band, such as 2 to 40 GHz, for example, and hence the noise figure (NF), which is the ratio between the input SN ratio and output SN ratio, deteriorates. Further, when resistive elements are formed on a silicon substrate, an impurity region is generally formed in the silicon substrate surface. However, a parasitic capacitance between the silicon substrate and the impurity region affects high frequency signals, which brings about degradation of the high frequency characteristic. In addition, switches SW1 and SW12 are provided in the transmission channel of the high frequency signal and therefore the characteristics of the transistor constituting these switches possess process dependency and so forth, which has an adverse effect on the linearity of the attenuator. Further, as shown in FIG. 2, the matching circuit 12 must be provided upstream of the attenuator 16 and brings about an increase in the number of elements.